1. Field of the Invention
The present invention generally relates to analog-to-digital converters (ADCs), and more particularly to a successive approximation register (SAR) ADC with binary error tolerance.
2. Description of the Prior Art
Flash analog-to-digital converter (ADC), pipelined ADC, and successive approximation register (SAR) ADC schemes embody widely used ADC architectures that have respective advantages in specific applications. The SAR ADC requires less power consumption and silicon area (and thus cost) as compared to other ADC architectures. Nevertheless, the SAR ADC needs more cycles to obtain the digital output, and therefore is not a good fit for high speed applications.
The SAR DAC is subdivided into two methods: binary approximation and non-binary approximation. The binary approximation ADC was disclosed, for example, in “A 65-fJ/Conversion-step 0.9-V 200-KS/s Rail-to-Rail 8-bit Successive Approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, October 2007, pp. 2161-2168, by Hao-Chiao Hong and Guo-Ming Lee, the disclosure of which is hereby incorporated by reference. In this disclosure, a digital-to-analog (DAC) is used to successively approximate a sampled signal, which is then compared by a comparator to determine whether setting or resetting next bit. This binary search continues several times with each voltage difference inversely proportional to 2n, until the equivalent digital output is obtained. The binary approximation was also disclosed, for example, in “A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7 mW 9b Charge-sharing SAR ADC in 90 nm Digital CMOS,” ISSCC Dig. Tech. Papers, February 2007, pp. 246-247, by J. Craninckx and G. van der Plas, the disclosure of which is hereby incorporated by reference. This disclosure applies the same operation principle as that discussed above, but uses a comparator to compare the charge difference in order to determine whether adding or subtracting further charge. This binary search continues several times with each charge difference inversely proportional to 2n, until the equivalent digital output is obtained. In the operation, the speed of the ADC of this binary approximation method is limited, because the comparator in either disclosure should wait for complete settling time until the voltage or charge is within the accuracy of ½LSB (that is, ½N+1, where N is the resolution of the ADC), otherwise, sampling error incurs.
The non-binary method was disclosed, for example, in “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-m CMOS,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 176-177, by F. Kuttner, the disclosure of which is hereby incorporated by reference. Contrary to the binary approximation, the voltage difference in the non-binary approximation method in not inversely proportional to 2n, but 1.85n. Owing to the capability of tolerating sampling error up to about 12.7%, this non-binary approximation method can sample an unstable signal, thereby reducing cycle time and data conversion time, however, at the cost of requiring additional and complex digital correction (e.g., logic circuit or read only memory (ROM)), and associated power consumption and silicon area.
For the reason that conventional approximation ADC architectures have respective disadvantages, a need has arisen to propose a novel ADC architecture that can maintain the advantages while avoid the disadvantages of conventional ADC architectures.